/*
	reg8.v
	Template for 8 bits register
	
	This project and file(s) are released under GNU GPL v3.
	Please find license file from root directory.
	Meng Sun (c) 2013 <leon.meng.sun@gmail.com>
*/

module reg8 (A, CLK, nRESET, EN, Y);

input [7:0] A;
input CLK, nRESET, EN;
output [7:0] Y;

wire [7:0] A;
wire CLK, nRESET, EN;
reg [7:0] Y;

always @ (posedge CLK or negedge nRESET)
begin
	if (nRESET == 0) /*Async-reset*/
	begin
		Y <= 8'b0;
	end else if (EN == 1) /*Latch input to output*/
	begin
		Y <= A;
	end
end

endmodule